Technical Q&A's

HW 25 - PCI Interrupts (15-July-95)

Q The PCI specification (section 6.2.4, page 159) says that the POST code is responsible for allocating the interrupt vectors for all PCI cards. The POST software writes the vector to the PCI "Interrupt Line" register associated with every card that has a non-zero PCI "Interrupt Pin".

Is this what the Mac implementation of the POST standard does?

A Open Firmware does not allocate interrupt vectors as in a typical x86 PC environment. Interrupts on PCI PowerMac CPUs are organized as 1 Interrupt per slot. At the motherboard connector, INTA#, INTB#, INTC#, and INTD# signals are tied together per slot and the resulting signal is called "SlotXInt#". Therefore, Open Firmware does not need to interrogate the Interrupt Line Register in Configuration Space.

The control and propagation of hardware interrupts are abstracted from the driver software. A interrupt source for a PCI card or device is represented by a node in a hierarchical tree, called Interrupt Source Tree (IST).

For a good description of Interrupts on PCI PowerMac CPUs, please refer to the Interrupt Management section in the Driver Services Library chapter in Designing PCI Cards and Drivers for Power Macintosh Computers, A8 draft or later.

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